Section: Software

FloPoCo

Participants : Florent Dinechin [correspondant] , Bogdan Pasca, Laurent-Stéphane Didier.

The purpose of the FloPoCo project is to explore the many ways in which the flexibility of the FPGA target can be exploited in the arithmetic realm. FloPoCo is a generator of operators written in C++ and outputting synthesizable VHDL automatically pipelined to an arbitrary frequency.

In 2011, FloPoCo was turned into a library which can be used as a back-end to high-level synthesis tools. An expression parser that generates a complete pipeline was also added for this context. The integer multiplier and floating-point adder were rewritten, and several new operators were added, including a floating-point power operator, and novel operators for integer and floating-point division by a constant.

Versions 2.2.0, 2.2.1, and 2.3.0 were released in 2011.

Among the known users of FloPoCo are U. Cape Town, U.T. Cluj-Napoca, Imperial College, U. Essex, U. Madrid, U. P. Milano, T.U. Muenchen, T. U. Kaiserslautern, U. Paderborn, CalTech, U. Pernambuco, U. Perpignan, U. Tokyo, Virginia Tech U. and several companies.

URL: http://flopoco.gforge.inria.fr/

• Version: 2.3.0 (december 2011)

• APP: IDDN.FR.001.400014.000.S.C.2010.000.20600 (version 2.0.0)

• License: specific, GPL-like.

• Type of human computer interaction: command-line interface, synthesisable VHDL output.

• OS/Middelware: Linux, Windows/Cygwin.

• Required library or software: MPFR, flex, Sollya.

• Programming language: C++.

• Documentation: online and command-line help, API in doxygen format, articles.